The present invention relates to an image signal processor for performing a predetermined signal process on an image signal output from a solid-state imaging device to generate an image signal complying with a predetermined format.
An imaging apparatus using a solid-state imaging device (CCD image sensor), such as a digital still camera, often uses a battery as a power supply. The range of the output voltage of a battery is limited. Therefore, a regulator circuit or a booster circuit is employed to drive the CCD image sensor.
FIG. 1 is a schematic block diagram of a prior art imaging apparatus 50. The imaging apparatus 50 includes a regulator circuit 2, which is located at the input side. The regulator circuit 2, which is supplied with power supply voltage (e.g., 3.2V) from a battery, generates a predetermined regulated voltage VK (e.g., 2.9V). The imaging apparatus 50 has a signal processor 7, which includes a signal processing circuit 9 and an output circuit 14. The regulated voltage VK is set in accordance with the operational voltage of the output circuit 14. The operational voltage of the output circuit 14 is greater than that of the signal processing circuit 9.
The CCD image sensor 3 is, for example, a frame transfer type, and includes an imaging section 3a, a charge section 3b, a horizontal transfer section 3c, and an output section 3d. The imaging section 3a has a plurality of light receiving pixels for accumulating information charges generated in accordance with an imaging subject. The charge section 3b temporarily stores the information charges corresponding to a single screen image that is retrieved from the imaging section 3a. The horizontal transfer section 3c sequentially retrieves the information charges from the charge section 3b and sequentially transfers the information charges in the horizontal direction in units of single pixels. The output section 3d receives information charges from the horizontal transfer section 3c, converts the information charges in units of single pixels to voltage values corresponding to the information charges, and generates an image signal Y(t). The image signal Y(t) is provided to the signal processor 7.
The drive device 4 includes a booster circuit 5 and a vertical driver 6, which are formed on the same semiconductor substrate. The booster circuit 5 includes a positive voltage generating charge pump and a negative voltage generating charge pump. The positive voltage generating charge pump increases the regulated voltage VK (e.g., 2.9V) to a predetermined positive voltage VOH (e.g., 5V) and supplies the positive voltage VOH to the CCD image sensor 3. The negative voltage generating charge pump boosts the regulated voltage VK to a predetermined negative voltage VOL (e.g., −5V) and supplies the negative voltage VOL to the vertical driver 6.
The vertical driver 6 operates with the negative voltage VOL and generates a frame transfer clock signal φf and a vertical transfer clock signal φv. The clock signals φf and φv are respectively provided to the imaging section 3a and the charge section 3b of the CCD image sensor 3. The frame transfer clock signal φf and the vertical transfer clock φv are generated in accordance with a frame shift timing signal FT, a vertical synchronizing signal VT, and a horizontal synchronizing signal HT, which are provided from the timing control circuit 13 of the signal processor 7. The information charges that are accumulated in the imaging section 3a are frame-transferred to the charge section 3b at a timing that is in accordance with the frame shift timing signal FT. The information charges that are accumulated in the charge section 3b are line-transferred to the horizontal transfer section 3c at a timing that is in accordance with the vertical synchronizing signal VT and the horizontal synchronizing signal HT.
A horizontal driver 8 operates with the regulated voltage VK and generates a horizontal transfer clock signal φh. The horizontal transfer clock signal φh is provided to the horizontal transfer section 3c of the CCD image sensor 3. The horizontal transfer clock signal φh is generated in accordance with the vertical synchronizing signal VT and the horizontal synchronizing signal HT, which are provided from the timing control circuit 13. The information charges retrieved in the horizontal transfer section 3c are sequentially and horizontally transferred in single pixel units at a timing that is in accordance with the horizontal synchronizing signal HT and converted to an image signal Y(t) by the output section 3d. 
The signal processing circuit 9, which includes an analog processing circuit 10, an A/D converter 11, and a digital processing circuit 12. The analog processing circuit 10 receives an image signal Y(t) from the CCD image sensor 3 and performs various types of analog signal processing, such as a sample and hold and gain adjustment. The A/D converter 11 receives an image signal, which has undergone an analog processing, converts the image signal (n) to a digital signal in single pixel units, and generates digital image data signal Y(n).
The digital processing circuit 12 performs a predetermined matrix processing on the digital image signal Y(n), generates luminance data and a chrominance data, performs processes such as contour correction and gamma correction on the luminance data, and generates image data signal Y′(n).
The timing control circuit 13, which operates with the regulated voltage VK supplied from the regulator circuit 2, divides a reference clock signal CK, which has a fixed cycle, and determines the vertical and horizontal scanning timing of the CCD image sensor 3. In accordance with the determined timing, the timing control circuit 13 generates the vertical synchronizing signal VT and the horizontal synchronizing signal HT. Further, the timing control circuit 13 generates the frame shift signal FT at a cycle coinciding with the cycle of the vertical synchronizing signal.
The output circuit 14 operates with the regulated voltage VK, receives the image data signal Y′(n) from the digital processing circuit 12 of the signal processing circuit 9, and provides the image data signal Y′(n) to external device including a central processing unit (CPU) 16, a memory 17, or a display driver 18 via a system bus 15. The CPU 16 centrally controls the operations of the imaging apparatus 50, the memory 17, and the display driver 18 in response to commands from peripheral devices. The memory 17 is a removable memory (e.g., a flash memory or memory card) or a fixed memory, such as a hard disk, and stores image data signal Y′(n), which is provided from the imaging apparatus 50. The display driver 18 receives the image data signal Y′(n) from the imaging apparatus 50, drives the display panel 19 to display a reproduced image.
In the signal processor 7 of the imaging apparatus 50, after the regulator circuit 2 regulates the power supply voltage VDD from the battery to the predetermined regulated voltage VK, every circuit of the signal processor 7 is commonly supplied with the regulated voltage VK. Thus, even though the power supply voltage, which is less that the regulated voltage VK, operates the signal processing circuit 9 the signal processing circuit 9 is supplied with the regulated voltage VK, which is greater than the operational voltage. As a result, the signal processing circuit 9 consumes unnecessary power. This may increase the power consumption of the imaging apparatus 50.